EPM3512AQC208-7 vs EPM3512AQC20810N Comparison

Detailed side-by-side comparison of EPM3512AQC208-7 by Intel and EPM3512AQC20810N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3512AQC20810N

EPM3512AQC20810N - MAX 3000A CPLD 512 Macro Cells 208-PQFP | Altera

EPM3512AQC20810N Nrnd

Specification Comparison

Parameter EPM3512AQC208-7 EPM3512AQC20810N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $41.72 $39.75
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 β€”
Usable Gates 10,000 10,000
Propagation Delay (tPD) 7.5 ns 10 ns
Counter Frequency (fCNT) 116.3 MHz β€”
User I/Os 172 172
Logic Elements / LEs N/A (CPLD macrocell architecture) β€”
Supply Voltage (VCCINT) 3.3 V β€”
I/O Standards Supported 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) β€”
Package 208-Pin PQFP (FQFP, gull-wing) 208-pin PQFP (Plastic Quad Flat Pack)
Operating Temperature 0 C to +70 C (commercial) [DATA_NEEDED: industrial/commercial grade range]
Programming In-System Programmable via JTAG (IEEE Std. 1532) β€”
Process Technology CMOS EEPROM, 0.30 um β€”
RoHS Status Compliant [DATA_NEEDED: lead-free/RoHS status]
Lead-Free Yes β€”
Macro Cells β€” 512
Logic Array Blocks (LABs) β€” 16
Core Voltage (VCCINT) β€” 3.3 V
I/O Voltage (VCCIO) β€” 3.3 V (5.0 V tolerant I/O)
Configuration Memory β€” EEPROM (non-volatile, instant-on)
Programming Interface β€” JTAG (IEEE 1149.1 / IEEE 1532 ISP)
Maximum Frequency β€” [DATA_NEEDED: fMAX]
Mounting Type β€” Surface Mount
MSL Level β€” [DATA_NEEDED: MSL rating]

Datasheets & Resources

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