EPM3512AQC208-7N vs EPM3512AQC208-10N Comparison

Detailed side-by-side comparison of EPM3512AQC208-7N by Altera and EPM3512AQC208-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3512AQC208-7N EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N ⚠ Last Time Buy

Specification Comparison

Parameter EPM3512AQC208-7N EPM3512AQC208-10N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $41.41 $42.80
Family MAX 3000A MAX 3000A
Logic Capacity 512 macrocells, 10,000 usable gates β€”
Logic Array Blocks (LABs) 32 16
Macrocells per LAB 16 β€”
User I/Os 172 172
Propagation Delay (tPD) 7.5 ns β€”
Maximum Frequency (fCNT) 116.3 MHz β€”
Supply Voltage (VCCINT) 3.3 V (3.0 V to 3.6 V) β€”
I/O Bank Count 4 (MultiVolt) β€”
Supported I/O Standards 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS β€”
Process Technology 0.30 Β΅m CMOS EEPROM CMOS EEPROM
Configuration Non-volatile EEPROM, in-system programmable (ISP) β€”
JTAG Interface IEEE 1149.1 BST + IEEE 1532 ISP β€”
Package 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) 208-pin PQFP (Plastic Quad Flat Pack)
Operating Temperature 0 Β°C to +70 Β°C (commercial) 0 C to 70 C (commercial)
RoHS Status Compliant [DATA_NEEDED: RoHS status not in verified web data]
Speed Grade -7 -10
Device Type β€” CPLD (Complex Programmable Logic Device)
Macrocells β€” 512
Usable Gates β€” Up to 10,000
Supply Voltage β€” 3.3 V
Pin-to-Pin Delay β€” 4.5 ns (-10 speed grade)
Maximum Internal Frequency β€” 227.3 MHz
In-System Programming β€” IEEE Std. 1149.1 JTAG, IEEE Std. 1532
Boundary-Scan Test (BST) β€” Built-in, IEEE 1149.1 compliant
I/O Standards β€” MultiVolt (1.8V / 2.5V / 3.3V)

Datasheets & Resources

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