EPM3512AQC20810 vs EPM3512AQC208-10N Comparison
Detailed side-by-side comparison of EPM3512AQC20810 by Altera and EPM3512AQC208-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM3512AQC20810 | EPM3512AQC208-10N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.80 | $42.80 |
| Family | MAX 3000A | MAX 3000A |
| Logic Type | CPLD (EEPROM-based, non-volatile) | β |
| Macro Cells | 512 | β |
| User I/Os | 172 | 172 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Usable Gates (equivalent) | 10000 | β |
| Package | 208-pin PQFP (PQ208) | 208-pin PQFP (Plastic Quad Flat Pack) |
| Speed Grade | -10 (tPD = 10 ns) | -10 |
| Propagation Delay (tPD) | 10 ns | β |
| Maximum Internal Frequency | 132 MHz | 227.3 MHz |
| Core Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Supply Voltage (VCCIO) | 3.3 V | β |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 3.3 V ISP) | β |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 compliant | β |
| Operating Temperature (commercial) | 0 Β°C to +70 Β°C | β |
| Process Technology | 0.30 Β΅m CMOS EEPROM | CMOS EEPROM |
| Configuration Memory | On-chip EEPROM, non-volatile, 100+ cycles, 10+ year retention | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status not in verified web data] |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macrocells | β | 512 |
| Usable Gates | β | Up to 10,000 |
| Supply Voltage | β | 3.3 V |
| Pin-to-Pin Delay | β | 4.5 ns (-10 speed grade) |
| In-System Programming | β | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Boundary-Scan Test (BST) | β | Built-in, IEEE 1149.1 compliant |
| I/O Standards | β | MultiVolt (1.8V / 2.5V / 3.3V) |
| Operating Temperature | β | 0 C to 70 C (commercial) |