EPM3512AQC20810 vs EPM3512AQC208-10S Comparison
Detailed side-by-side comparison of EPM3512AQC20810 by Altera and EPM3512AQC208-10S by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM3512AQC20810 | EPM3512AQC208-10S |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.80 | $9.75 |
| Family | MAX 3000A | MAX 3000A |
| Logic Type | CPLD (EEPROM-based, non-volatile) | β |
| Macro Cells | 512 | β |
| User I/Os | 172 | 208 |
| Logic Array Blocks (LABs) | 16 | 32 (16 macrocells each) |
| Usable Gates (equivalent) | 10000 | β |
| Package | 208-pin PQFP (PQ208) | 208-pin FineLine BGA-256 |
| Speed Grade | -10 (tPD = 10 ns) | -10 (tPD1 = 7.5 ns) |
| Propagation Delay (tPD) | 10 ns | β |
| Maximum Internal Frequency | 132 MHz | β |
| Core Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Supply Voltage (VCCIO) | 3.3 V | β |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 3.3 V ISP) | β |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 compliant | Yes (PCI Local Bus Specification Rev 2.2) |
| Operating Temperature (commercial) | 0 Β°C to +70 Β°C | β |
| Process Technology | 0.30 Β΅m CMOS EEPROM | EEPROM-based CMOS |
| Configuration Memory | On-chip EEPROM, non-volatile, 100+ cycles, 10+ year retention | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs_status] |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macrocells | β | 512 |
| Usable Gates | β | 1750 |
| Propagation Delay (tPD1) | β | 7.5 ns (pin-to-pin) |
| Supply Voltage - VCCINT (internal) | β | 3.3 V |
| Supply Voltage - VCCIO (I/O) | β | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) |
| Programming Technology | β | CMOS EEPROM |
| In-System Programmability (ISP) | β | Yes (IEEE Std. 1149.1 JTAG) |
| Operating Temperature | β | 0C to +70C (commercial) |
| Boundary-Scan (JTAG) | β | Yes (1149.1 compliant) |
| Program/Erase Endurance | β | 100 cycles minimum |
| Logic Family | β | CMOS |