EPM3512AQC20810N vs EPM3512AQC208-7N Comparison

Detailed side-by-side comparison of EPM3512AQC20810N by Altera and EPM3512AQC208-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3512AQC208-7N EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N ⚠ Last Time Buy

Specification Comparison

Parameter EPM3512AQC20810N EPM3512AQC208-7N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $39.75 $41.41
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Macro Cells 512 β€”
Usable Gates 10,000 β€”
User I/Os 172 172
Logic Array Blocks (LABs) 16 32
Propagation Delay (tPD) 10 ns 7.5 ns
Core Voltage (VCCINT) 3.3 V β€”
I/O Voltage (VCCIO) 3.3 V (5.0 V tolerant I/O) β€”
Package 208-pin PQFP (Plastic Quad Flat Pack) 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing)
Configuration Memory EEPROM (non-volatile, instant-on) β€”
Programming Interface JTAG (IEEE 1149.1 / IEEE 1532 ISP) β€”
Maximum Frequency [DATA_NEEDED: fMAX] β€”
Operating Temperature [DATA_NEEDED: industrial/commercial grade range] 0 Β°C to +70 Β°C (commercial)
RoHS Status [DATA_NEEDED: lead-free/RoHS status] Compliant
Mounting Type Surface Mount β€”
MSL Level [DATA_NEEDED: MSL rating] β€”
Logic Capacity β€” 512 macrocells, 10,000 usable gates
Macrocells per LAB β€” 16
Maximum Frequency (fCNT) β€” 116.3 MHz
Supply Voltage (VCCINT) β€” 3.3 V (3.0 V to 3.6 V)
I/O Bank Count β€” 4 (MultiVolt)
Supported I/O Standards β€” 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS
Process Technology β€” 0.30 Β΅m CMOS EEPROM
Configuration β€” Non-volatile EEPROM, in-system programmable (ISP)
JTAG Interface β€” IEEE 1149.1 BST + IEEE 1532 ISP
Speed Grade β€” -7

Datasheets & Resources

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