EPM3512AQC210-10 vs EPM3256AQC208-10 Comparison
Detailed side-by-side comparison of EPM3512AQC210-10 by Altera and EPM3256AQC208-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3256AQC208-10 - MAX 3000A CPLD 256 Macrocells 10ns 208-PQFP | Intel / Altera
EPM3256AQC208-10 ObsoleteSpecification Comparison
| Parameter | EPM3512AQC210-10 | EPM3256AQC208-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $25.40 | $15.20 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Logic Macrocells | 512 | β |
| Logic Array Blocks (LABs) | 16 (32 macrocells each) | β |
| Maximum User I/O Pins | 172 | β |
| Speed Grade | -10 (10 ns tPD) | β |
| Pin-to-Pin Propagation Delay (tPD1, max) | 10 ns | β |
| Maximum Operating Frequency (fCNT) | 125 MHz | β |
| Supply Voltage - Core (VCCINT) | 3.3 V | β |
| Supply Voltage - I/O (VCCIO) | 3.3 V or 2.5 V | β |
| Input Voltage Tolerance | 5.0 V tolerant | β |
| Programmable Technology | EEPROM (in-system programmable) | β |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | IEEE 1149.1 JTAG (ISP) |
| Package | PQFP-210 | 208-BFQFP (PQFP, Gull Wing) |
| Operating Temperature | 0C to +70C (commercial) | 0 Β°C to +70 Β°C (Commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: rohs_compliance_status] | [DATA_NEEDED: RoHS status] |
| Logic Family | β | CMOS (EEPROM-based) |
| Macrocells | β | 256 |
| Usable Gates | β | 5,000 |
| User I/Os | β | 161 |
| Number of Pins | β | 208 |
| Pin-to-Pin Propagation Delay | β | 10 ns |
| Counter Frequency (max) | β | 227.3 MHz |
| Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Tolerance | β | MultiVolt 2.5 V / 3.3 V / 5.0 V tolerant |
| PCI-SIG Compliance | β | Yes (speed grades -4, -5, -6, -7, -10) |
| Global Clock Networks | β | 4 (CLK, CLR, OE, GCLK) |