EPM3512AQC210-10 vs EPM3512AQC208-10 Comparison

Detailed side-by-side comparison of EPM3512AQC210-10 by Altera and EPM3512AQC208-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC210-10 EPM3512AQC208-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $25.40 $22.10
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Logic Macrocells 512 β€”
Logic Array Blocks (LABs) 16 (32 macrocells each) 32
Maximum User I/O Pins 172 β€”
Speed Grade -10 (10 ns tPD) β€”
Pin-to-Pin Propagation Delay (tPD1, max) 10 ns β€”
Maximum Operating Frequency (fCNT) 125 MHz β€”
Supply Voltage - Core (VCCINT) 3.3 V β€”
Supply Voltage - I/O (VCCIO) 3.3 V or 2.5 V β€”
Input Voltage Tolerance 5.0 V tolerant β€”
Programmable Technology EEPROM (in-system programmable) β€”
Programming Interface JTAG (IEEE 1149.1) / ISP β€”
Package PQFP-210 208-pin PQFP
Operating Temperature 0C to +70C (commercial) 0C to +70 C (commercial)
Mounting Type Surface Mount β€”
RoHS Status [DATA_NEEDED: rohs_compliance_status] [DATA_NEEDED: RoHS status not in verified data]
Usable Gates β€” 10,000
Macrocells β€” 512
User I/Os β€” 208
Propagation Delay (tPD) β€” 7.5 ns
Maximum Frequency (fCNT) β€” 116.3 MHz
Supply Voltage (VCCINT) β€” 3.3 V
Configuration Memory β€” EEPROM (non-volatile)
In-System Programmability β€” Yes (IEEE Std. 1532)
JTAG Boundary Scan β€” Yes (IEEE 1149.1)
PCI Compliance β€” PCI Local Bus Spec Rev. 2.2 (-10 speed grade)

Datasheets & Resources

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