EPM3512AQI208-10N vs EPM3512AQC208-10-10N Comparison

Detailed side-by-side comparison of EPM3512AQI208-10N by Intel and EPM3512AQC208-10-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQI208-10N EPM3512AQC208-10-10N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $12.90 $31.20
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Logic Family CMOS EEPROM-based β€”
Macro Cells 512 β€”
Logic Array Blocks (LABs) 12 β€”
User I/Os 172 (max), 208-pin package 172
Propagation Delay (tPD) 10 ns 10 ns (-10 speed grade)
Supply Voltage 3.3 V β€”
I/O Standards MultiVolt (2.5 V / 3.3 V / 5 V tolerant) β€”
Package Type PQFP-208 (FINE LINE BGA-style 256-pin land) β€”
Pins 256 (package), 208 used β€”
Operating Temperature 0C to 70C 0 Β°C to +70 Β°C (commercial)
Mounting Type Surface Mount Surface Mount
Programming Interface JTAG (IEEE 1149.1) / ISP (IEEE 1532) β€”
Compliance RoHS status unknown from data β€”
Boundary Scan Built-in BST (IEEE 1149.1) β€”
Configuration Memory On-chip EEPROM, non-volatile β€”
Macrocells β€” 512
Usable Gates β€” 10,000
Logic Elements / LABs β€” 16 Logic Array Blocks
Maximum Frequency (fCNT) β€” 87 MHz
Supply Voltage - Core (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 2.5 V / 3.3 V / 5.0 V
Process Technology β€” CMOS EEPROM
In-System Programmability β€” Yes, IEEE Std. 1532 compliant
Boundary-Scan (JTAG) β€” Yes, IEEE 1149.1
PCI-SIG Compliance β€” PCI Local Bus Specification Rev 2.2 (at -10 speed grade)
Package β€” 208-pin PQFP (Plastic Quad Flat Pack)
Lead-Free / RoHS β€” [DATA_NEEDED: RoHS status]

Datasheets & Resources

Browse All Products Create BOM Request Quote