EPM3512AQI20810 vs EPM3512AQC208-10S Comparison

Detailed side-by-side comparison of EPM3512AQI20810 by Intel and EPM3512AQC208-10S by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQI20810 EPM3512AQC208-10S
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $21.10 $9.75
Family MAX 3000A MAX 3000A
Macrocells 512 512
Usable Gates 10,000 1750
Logic Array Blocks (LABs) 16 (32 macrocells each) 32 (16 macrocells each)
Maximum User I/O Pins 172 β€”
Pin-to-Pin Propagation Delay (tPD) 10 ns β€”
Internal fMAX (logic feedback) 87 MHz β€”
Supply Voltage (VCCINT) 3.0 V to 3.6 V β€”
MultiVolt I/O Interface 1.8 V / 2.5 V / 3.3 V / 5.0 V compatible β€”
Package 208-pin PQFP (PQ208) 208-pin FineLine BGA-256
Mounting Type Surface Mount β€”
Process Technology 0.30 Β΅m CMOS EEPROM EEPROM-based CMOS
In-System Programmability IEEE Std. 1149.1 JTAG + IEEE Std. 1532 β€”
Operating Temperature -40 Β°C to +85 Β°C (Industrial, "I" suffix) 0C to +70C (commercial)
Lead-Free / RoHS Contains lead / RoHS non-compliant (per Altera datasheet marking) β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
User I/Os β€” 208
Speed Grade β€” -10 (tPD1 = 7.5 ns)
Propagation Delay (tPD1) β€” 7.5 ns (pin-to-pin)
Supply Voltage - VCCINT (internal) β€” 3.3 V
Supply Voltage - VCCIO (I/O) β€” 2.5 V, 3.3 V, or 5.0 V (MultiVolt)
Programming Technology β€” CMOS EEPROM
In-System Programmability (ISP) β€” Yes (IEEE Std. 1149.1 JTAG)
PCI Compliance β€” Yes (PCI Local Bus Specification Rev 2.2)
Boundary-Scan (JTAG) β€” Yes (1149.1 compliant)
Program/Erase Endurance β€” 100 cycles minimum
Logic Family β€” CMOS
RoHS Status β€” [DATA_NEEDED: rohs_status]

Datasheets & Resources

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