EPM5032DC-15 vs EPM5032DC-2 Comparison
Detailed side-by-side comparison of EPM5032DC-15 by Altera and EPM5032DC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5032DC-15 - 600-Gate, 32-Macrocell UV PLD | Altera MAX 5000 | DIP-28
EPM5032DC-15 Obsolete
Specification Comparison
| Parameter | EPM5032DC-15 | EPM5032DC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $8.75 |
| Family | MAX 5000 | β |
| Device Type | UV-erasable EPLD (PAL-type CMOS) | β |
| Usable Gates | 600 | β |
| Macrocells | 32 | 32 |
| Propagation Delay (tPD) | 15 ns | β |
| Maximum Toggle Frequency (fMAX) | 83.3 MHz | β |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V (single supply, +/-5%) |
| Logic Family | CMOS, TTL-compatible I/O | β |
| Programmable Pins | 16 bidirectional I/O + 4 dedicated input = 20 | β |
| Total Package Pins | 28 | β |
| Package | CERDIP-28 (windowed, through-hole) | 20-pin CDIP (Ceramic DIP) |
| Mounting Type | Through-Hole (DIP) | Through-Hole (DIP) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial grade) |
| Erasure Method | UV light through ceramic quartz window | β |
| Process Technology | CMOS | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] |
| Lead-Free | unknown | β |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Series | β | MAX 5000 |
| Usable Gates (typical) | β | 600 |
| Logic Array Blocks (LABs) | β | 4 |
| Speed Grade | β | -2 (tPD ~25 ns, commercial) |
| Configuration Memory | β | EPROM (one-time programmable per generation; UV-erasable variants exist) |
| Programmable Pins / I/O | β | 20 pins (JEDEC-standard 0.300" ceramic DIP) |
| Programming Interface | β | Altera ByteBlaster / parallel-port JTAG-style ISP |
| Interconnect | β | Programmable Interconnect Array (PIA) with deterministic timing |
| MSL Level | β | Not applicable (through-hole hermetic ceramic) |