EPM5032DC-2 vs EPM5128GC Comparison
Detailed side-by-side comparison of EPM5032DC-2 by Altera and EPM5128GC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032DC-2 | EPM5128GC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.75 | $19.20 |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Series | MAX 5000 | β |
| Macrocells | 32 | 128 |
| Usable Gates (typical) | 600 | β |
| Logic Array Blocks (LABs) | 4 | β |
| Package | 20-pin CDIP (Ceramic DIP) | β |
| Speed Grade | -2 (tPD ~25 ns, commercial) | β |
| Configuration Memory | EPROM (one-time programmable per generation; UV-erasable variants exist) | Non-volatile UV-EPROM (windowed ceramic) |
| Supply Voltage (VCC) | 5 V (single supply, +/-5%) | β |
| Operating Temperature | 0C to +70C (commercial grade) | β |
| Programmable Pins / I/O | 20 pins (JEDEC-standard 0.300" ceramic DIP) | β |
| Programming Interface | Altera ByteBlaster / parallel-port JTAG-style ISP | β |
| Interconnect | Programmable Interconnect Array (PIA) with deterministic timing | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] | [DATA_NEEDED: RoHS compliance] |
| Mounting Type | Through-Hole (DIP) | Through-Hole (PGA socket required) |
| MSL Level | Not applicable (through-hole hermetic ceramic) | β |
| Family | β | MAX 5000 |
| Usable Gates | β | 2,500 |
| Logic Elements / LABs | β | [DATA_NEEDED: LAB count] |
| User I/Os | β | 68 |
| Package Type | β | WPGA (Windowed Ceramic Pin Grid Array) |
| Package Code | β | WPGA |
| Number of Terminals | β | 68 |
| Terminal Form | β | PIN/PEG (through-hole PGA with alignment pegs) |
| Package Shape | β | Square |
| Temperature Grade | β | Commercial |
| Supply Voltage (Vcc) | β | 5 V |
| Process Technology | β | CMOS, UV-erasable |
| Architecture | β | EPLD, programmable AND/OR array with fixed OR plane |
| Propagation Delay (tpd) | β | [DATA_NEEDED: tpd in ns] |
| Maximum Frequency (fmax) | β | [DATA_NEEDED: fmax in MHz] |
| Programmable Security Bit | β | Yes |