EPM5032DC-25 vs EPM5032DI-20 Comparison
Detailed side-by-side comparison of EPM5032DC-25 by Altera and EPM5032DI-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032DC-25 | EPM5032DI-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $3.55 | $8.75 |
| Manufacturer | Altera (Intel Programmable Solutions Group) | β |
| Product Family | MAX 5000 | β |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | β |
| Macrocells | 32 | 32 |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | β |
| Maximum Counter Frequency (fCNT) | [DATA_NEEDED: maximum counter frequency] | β |
| Setup Time (tSU) | [DATA_NEEDED: setup time] | β |
| Number of Dedicated Inputs | 32 (in DIP-28 pinout) | β |
| Number of I/O Pins | 22 (in DIP-28 pinout, 4 used as dedicated inputs) | β |
| Package | CDIP-28 (Windowed Ceramic DIP-28) | Ceramic DIP-20 (windowed, UV-erasable) |
| Process Technology | CMOS, EPROM (UV-Erasable) | β |
| Architecture | PAL-Type, Single-LAB, 32-Macrocell | CMOS PAL-type EPLD with PIA |
| Output Structure | Programmable I/O with output enable | β |
| Flip-Flop Configuration | D, T, JK, or SR (programmable) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | Industrial (per 'I' suffix) |
| RoHS Status | Lead Free / RoHS Compliant (per distributor listings) | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] |
| Programming Method | UV erase + Altera/Intel MAX+PLUS II programmer | β |
| Erasure Method | UV light through ceramic window | β |
| Family | β | MAX 5000 (Altera legacy EPLD) |
| Dedicated Inputs | β | 7 |
| Bidirectional I/O Pins | β | 16 |
| Product Terms | β | 320 (maximum) |
| Flip-Flops | β | 16 (one per macrocell) |
| Maximum Clock Frequency | β | 62.5 MHz |
| Pin-to-Pin Delay | β | 20 ns (speed grade -20) |
| Programming | β | UV-erasable CMOS, JEDEC fuse file |
| Development Tool | β | Altera MAX+PLUS II (legacy) |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |