EPM5032DC vs EPM5032DC20 Comparison

Detailed side-by-side comparison of EPM5032DC by Altera and EPM5032DC20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5032DC EPM5032DC20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $10.40 $8.20
Family MAX 5000 β€”
Device Type EPLD (Erasable Programmable Logic Device) β€”
Macrocells 32 32
Logic Array Blocks (LABs) 1 β€”
Package DIP-24 (ceramic, windowed) 20-pin Ceramic DIP (DC) with UV window
Speed Grade DC (commercial) β€”
Operating Temperature 0C to +70C [DATA_NEEDED: operating temperature range]
Technology Bipolar EPROM, UV-erasable β€”
Programmable Logic Elements AND array + fixed OR array per macrocell β€”
Configuration Memory EPROM (UV-erasable via package window) β€”
Mounting Type Through-hole (DIP) Through-Hole (DIP)
Pin Count 24 β€”
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Programming Tool Altera MAX+PLUS II / A+PLUS legacy β€”
Lifecycle Status Obsolete (mature legacy) β€”
Device Family β€” MAX 5000
Product Type β€” UV-erasable PLD (CPLD class)
Usable Gates β€” 600
Propagation Delay (tPD) β€” 20 ns
Maximum Frequency (Fmax) β€” 71.4 MHz
Supply Voltage (VCC) β€” 5 V (4.75 V to 5.25 V)
Dedicated Inputs β€” 7
I/O Pins β€” 16 (bidirectional)
Total Inputs (max) β€” 24
Output Macrocells β€” 16
Clock Inputs β€” 1 (global)
Architecture β€” PAL-type with Programmable Interconnect Array (PIA)
Process Technology β€” CMOS

Datasheets & Resources

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