EPM5032DI-20 vs EPM5032DC20 Comparison
Detailed side-by-side comparison of EPM5032DI-20 by Intel and EPM5032DC20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032DI-20 | EPM5032DC20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.75 | $8.20 |
| Family | MAX 5000 (Altera legacy EPLD) | β |
| Architecture | CMOS PAL-type EPLD with PIA | PAL-type with Programmable Interconnect Array (PIA) |
| Macrocells | 32 | 32 |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | β |
| Product Terms | 320 (maximum) | β |
| Flip-Flops | 16 (one per macrocell) | β |
| Maximum Clock Frequency | 62.5 MHz | β |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | β |
| Package | Ceramic DIP-20 (windowed, UV-erasable) | 20-pin Ceramic DIP (DC) with UV window |
| Operating Temperature | Industrial (per 'I' suffix) | [DATA_NEEDED: operating temperature range] |
| Programming | UV-erasable CMOS, JEDEC fuse file | β |
| Development Tool | Altera MAX+PLUS II (legacy) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Device Family | β | MAX 5000 |
| Product Type | β | UV-erasable PLD (CPLD class) |
| Usable Gates | β | 600 |
| Propagation Delay (tPD) | β | 20 ns |
| Maximum Frequency (Fmax) | β | 71.4 MHz |
| Supply Voltage (VCC) | β | 5 V (4.75 V to 5.25 V) |
| I/O Pins | β | 16 (bidirectional) |
| Total Inputs (max) | β | 24 |
| Output Macrocells | β | 16 |
| Clock Inputs | β | 1 (global) |
| Process Technology | β | CMOS |
| Mounting Type | β | Through-Hole (DIP) |