EPM5032DI-25 vs EPM5032DC Comparison

Detailed side-by-side comparison of EPM5032DI-25 by Altera and EPM5032DC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5032DI-25 EPM5032DC
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $18.20 $10.40
Family MAX 5000 MAX 5000
Device Type UV-erasable Programmable Logic Device (PLD) EPLD (Erasable Programmable Logic Device)
Architecture PAL-type, CMOS, AND-OR sum-of-products β€”
Macrocells 32 32
Product Terms 320 β€”
Logic Gates [DATA_NEEDED: equivalent gate count] β€”
Dedicated Inputs 7 β€”
Bidirectional I/O Pins 16 β€”
Total Array Inputs 24 β€”
Registered Outputs 16 β€”
Global Clocks 1 β€”
Propagation Delay (tPD) 25 ns β€”
Maximum Clock Frequency (fMAX) 62.5 MHz β€”
Supply Voltage 5 V β€”
Process Technology CMOS β€”
Package Ceramic DIP, windowed (UV-erasable) DIP-24 (ceramic, windowed)
Pin Count [DATA_NEEDED: exact pin count - 24 or 28] 24
Operating Temperature 0C to +70C (commercial) 0C to +70C
I/O Standard TTL-compatible β€”
Programmability UV-erasable, EPROM-based β€”
Development Tool MAX+PLUS II / A+PLUS β€”
RoHS Status [DATA_NEEDED: likely non-compliant due to ceramic DIP] [DATA_NEEDED: RoHS status]
Lifecycle Not Recommended for New Designs (NRND) β€”
Logic Array Blocks (LABs) β€” 1
Speed Grade β€” DC (commercial)
Technology β€” Bipolar EPROM, UV-erasable
Programmable Logic Elements β€” AND array + fixed OR array per macrocell
Configuration Memory β€” EPROM (UV-erasable via package window)
Mounting Type β€” Through-hole (DIP)
Programming Tool β€” Altera MAX+PLUS II / A+PLUS legacy
Lifecycle Status β€” Obsolete (mature legacy)

Datasheets & Resources

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