EPM5032DI25 vs EPM5032JC Comparison
Detailed side-by-side comparison of EPM5032DI25 by Altera and EPM5032JC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032DI25 | EPM5032JC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $11.10 | $13.50 |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | UV-erasable EPLD (CMOS EPROM-based) | β |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 2 | β |
| Product Terms | 320 | β |
| Output Macrocells | 16 | β |
| Bidirectional I/O Pins | 16 | β |
| Dedicated Inputs | 7 | β |
| Total Inputs | 24 | β |
| Pin-to-Pin Delay (tPD) | 25 ns | β |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | β |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V |
| I/O Standard | TTL-compatible | β |
| Package | 24-pin Ceramic DIP (DI) with quartz window | PLCC-44 |
| Programming Technology | UV-EPROM (erasable via quartz window) | β |
| Logic Gates | β | 600 usable gates |
| Maximum I/O Pins | β | 40 |
| Propagation Delay (tPD) | β | [DATA_NEEDED: specific speed grade value] |
| Input Type | β | TTL-compatible |
| Output Type | β | TTL/CMOS-compatible |
| Operating Temperature | β | 0C to +70C (commercial) |
| Mounting Type | β | Surface Mount (J-lead) |
| Programmability | β | UV-erasable (windowed ceramic) / OTP variants |
| Design Software | β | MAX+PLUS II / Quartus legacy |
| JEDEC Standard | β | JEDEC PLCC-44 footprint |
| RoHS Status | β | unknown |
| Lead-Free | β | unknown |