EPM5032JC-20 vs EPM5032JC Comparison
Detailed side-by-side comparison of EPM5032JC-20 by Altera and EPM5032JC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5032JC-20
EPM5032JC-20 - 32-Macrocell UV PLD, 20ns, 24 Inputs | Altera
EPM5032JC-20 ObsoleteSpecification Comparison
| Parameter | EPM5032JC-20 | EPM5032JC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $13.50 |
| Product Type | UV-erasable Programmable Logic Device (PLD) | β |
| Family | MAX 5000 | MAX 5000 EPLD |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | β |
| Product Terms (P-terms) | 320 | β |
| Propagation Delay (tPD) | 20 ns | [DATA_NEEDED: specific speed grade value] |
| Maximum Clock Frequency | 62.5 MHz | β |
| Setup Time | 10 ns | β |
| I/O Lines | 16 (bidirectional) | β |
| Dedicated Inputs | 8 | β |
| Total Inputs | 24 | β |
| Package | 68-pin JLCC (windowed ceramic) | PLCC-44 |
| Process Technology | CMOS | β |
| Erase Method | UV (12V VPP + ultraviolet exposure) | β |
| Programming Voltage (VPP) | 12 V | β |
| Architecture | PAL-type AND-OR array with PIA interconnect | β |
| Lifecycle Status | Obsolete (legacy Altera MAX 5000) | β |
| Logic Gates | β | 600 usable gates |
| Maximum I/O Pins | β | 40 |
| Supply Voltage (VCC) | β | 5 V |
| Input Type | β | TTL-compatible |
| Output Type | β | TTL/CMOS-compatible |
| Operating Temperature | β | 0C to +70C (commercial) |
| Mounting Type | β | Surface Mount (J-lead) |
| Programmability | β | UV-erasable (windowed ceramic) / OTP variants |
| Design Software | β | MAX+PLUS II / Quartus legacy |
| JEDEC Standard | β | JEDEC PLCC-44 footprint |
| RoHS Status | β | unknown |
| Lead-Free | β | unknown |