EPM5032JC-20 vs EPM5032LC-25 Comparison
Detailed side-by-side comparison of EPM5032JC-20 by Altera and EPM5032LC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032JC-20 | EPM5032LC-25 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $8.20 |
| Product Type | UV-erasable Programmable Logic Device (PLD) | β |
| Family | MAX 5000 | β |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | β |
| Product Terms (P-terms) | 320 | β |
| Propagation Delay (tPD) | 20 ns | 25 ns |
| Maximum Clock Frequency | 62.5 MHz | β |
| Setup Time | 10 ns | β |
| I/O Lines | 16 (bidirectional) | β |
| Dedicated Inputs | 8 | 7 |
| Total Inputs | 24 | 24 (7 dedicated + 16 I/O used as input) |
| Package | 68-pin JLCC (windowed ceramic) | 28-pin PLCC (JEDEC S-PQCC-J28), 1.27 mm pitch |
| Process Technology | CMOS | β |
| Erase Method | UV (12V VPP + ultraviolet exposure) | β |
| Programming Voltage (VPP) | 12 V | β |
| Architecture | PAL-type AND-OR array with PIA interconnect | PAL-type EPLD (Erasable Programmable Logic Device) |
| Lifecycle Status | Obsolete (legacy Altera MAX 5000) | β |
| Device Family | β | MAX 5000 |
| Technology | β | CMOS, UV-erasable / OTP |
| Product Terms | β | 320 |
| I/O Pins | β | 16 bidirectional |
| Maximum Internal Frequency | β | 62.5 MHz |
| Supply Voltage (VCC) | β | 5 V Β±10% (4.5 V to 5.5 V) |
| I/O Standard | β | 5 V CMOS |
| Operating Temperature | β | 0 Β°C to +70 Β°C (commercial, "LC" suffix) |
| Mounting Type | β | Surface Mount, socket-compatible |
| Configuration Cell | β | Programmable interconnect array (PIA), OTP / UV-erasable |
| RoHS Status | β | Not RoHS compliant (legacy Altera product) |