EPM5032JC vs EPM5064JC-1 Comparison

Detailed side-by-side comparison of EPM5032JC by Altera and EPM5064JC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5032JC EPM5064JC-1
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $13.50 $18.25
Family MAX 5000 EPLD MAX 5000
Macrocells 32 β€”
Logic Gates 600 usable gates β€”
Maximum I/O Pins 40 β€”
Propagation Delay (tPD) [DATA_NEEDED: specific speed grade value] β€”
Supply Voltage (VCC) 5 V 5 V nominal (4.75 V – 5.25 V)
Input Type TTL-compatible β€”
Output Type TTL/CMOS-compatible β€”
Package PLCC-44 44-pin PLCC (J-lead, windowed ceramic)
Operating Temperature 0C to +70C (commercial) 0 Β°C to +70 Β°C (commercial, -JC suffix)
Mounting Type Surface Mount (J-lead) Surface Mount (PLCC socket recommended)
Programmability UV-erasable (windowed ceramic) / OTP variants β€”
Design Software MAX+PLUS II / Quartus legacy β€”
JEDEC Standard JEDEC PLCC-44 footprint β€”
RoHS Status unknown Non-compliant (windowed ceramic, contains Pb in glass frit)
Lead-Free unknown β€”
Device Type β€” EPLD (Erasable Programmable Logic Device)
Macro Cells β€” 64
Usable Gates β€” 1250 (typical)
Logic Elements β€” 128 (Logic Array Blocks)
Maximum Operating Frequency β€” 33.3 MHz (fCNT)
Pin-to-Pin Delay (tPD) β€” [DATA_NEEDED: tPD typical/max in ns]
Process Technology β€” 0.8 Β΅m CMOS
Programmable Pins β€” 36 (typical I/O, 44-pin PLCC)
Dedicated Inputs β€” [DATA_NEEDED: dedicated input count]
Erasure Method β€” UV-erasable through quartz window
Programming Method β€” Altera Logic Programmer + MasterBlaster/ByteBlasterMV
JTAG Boundary Scan β€” Not supported (classic MAX architecture)
Military/Avionics SMD β€” 5962-01-417-3750 (QML variant: EPM5064JM/883)

Datasheets & Resources

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