EPM5032JC25 vs EPM5064JC Comparison

Detailed side-by-side comparison of EPM5032JC25 by Altera and EPM5064JC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM5032JC25

EPM5032JC25 - 32-Macrocell MAX 5000 EPLD, 25ns | Altera

EPM5032JC25 Obsolete

Specification Comparison

Parameter EPM5032JC25 EPM5064JC
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $23.95 $7.10
Family MAX 5000 MAX 5000
Device EPM5032 β€”
Logic Elements 32 macrocells β€”
Propagation Delay (tPD) 25 ns β€”
Maximum Internal Frequency 62.5 MHz β€”
Product Terms 320 β€”
Flip-Flops 32 β€”
Dedicated Inputs 7 β€”
Bidirectional I/O Pins 16 β€”
Total Inputs to Array 24 β€”
Number of Outputs 16 β€”
Architecture PAL-type macrocells with global Programmable Interconnect Array (PIA) β€”
Technology CMOS EPROM, UV-erasable (windowed) / OTP β€”
Supply Voltage 5 V (TTL-level I/O) β€”
Package 28-pin PLCC (JC) 68-pin PLCC (JEDEC)
Mounting Type Surface Mount Surface Mount (socketed)
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Device Type β€” EPLD (Erasable PLD)
Macrocells β€” 64
Usable Gates β€” 1,250 (approx.)
Logic Array Inputs β€” 36
Logic Array Outputs β€” 64
Supply Voltage (VCC) β€” 5 V (typical, 4.75 V - 5.25 V range)
I/O Logic Level β€” TTL / CMOS compatible
Configuration Memory β€” EPROM (UV-erasable window or OTP)
Operating Temperature β€” [DATA_NEEDED: operating temperature grade]
Pin-to-Pin Delay (tPD) β€” [DATA_NEEDED: specific tPD grade value]
Maximum Frequency (fMAX) β€” [DATA_NEEDED: fCNT grade value]
Lead-Free β€” [DATA_NEEDED: lead-free status]
MSL Level β€” [DATA_NEEDED: MSL rating]
Programming Tool β€” Altera MAX+PLUS II / Quartus II (legacy device support)

Datasheets & Resources

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