EPM5032LC-15 vs EPM5032JC-20 Comparison
Detailed side-by-side comparison of EPM5032LC-15 by Altera and EPM5032JC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032LC-15 | EPM5032JC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.20 | $9.75 |
| Family | MAX 5000 EPLD | MAX 5000 |
| Architecture | PAL-type AND/OR with PIA | PAL-type AND-OR array with PIA interconnect |
| Usable Gates | 600 | β |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 4 | 1 |
| Dedicated Inputs | 7 | 8 |
| Bidirectional I/O Pins | 16 | β |
| Maximum Operating Frequency | 83.3 MHz | β |
| Pin-to-Pin Delay (tPD) | 15 ns | β |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | β |
| Technology | CMOS EPROM, 1.0 um process | β |
| Programmability | UV-Erasable / OTP | β |
| Package | JLCC-28 (windowed ceramic) | 68-pin JLCC (windowed ceramic) |
| Operating Temperature | 0C to +70C (commercial) | β |
| RoHS Status | Non-compliant (contains Pb, ceramic-windowed package) | β |
| Product Type | β | UV-erasable Programmable Logic Device (PLD) |
| Product Terms (P-terms) | β | 320 |
| Propagation Delay (tPD) | β | 20 ns |
| Maximum Clock Frequency | β | 62.5 MHz |
| Setup Time | β | 10 ns |
| I/O Lines | β | 16 (bidirectional) |
| Total Inputs | β | 24 |
| Process Technology | β | CMOS |
| Erase Method | β | UV (12V VPP + ultraviolet exposure) |
| Programming Voltage (VPP) | β | 12 V |
| Lifecycle Status | β | Obsolete (legacy Altera MAX 5000) |