EPM5032LC-15 vs EPM5032LC-25 Comparison

Detailed side-by-side comparison of EPM5032LC-15 by Altera and EPM5032LC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5032LC-15 EPM5032LC-25
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $8.20 $8.20
Family MAX 5000 EPLD β€”
Architecture PAL-type AND/OR with PIA PAL-type EPLD (Erasable Programmable Logic Device)
Usable Gates 600 β€”
Macrocells 32 32
Logic Array Blocks (LABs) 4 β€”
Dedicated Inputs 7 7
Bidirectional I/O Pins 16 β€”
Maximum Operating Frequency 83.3 MHz β€”
Pin-to-Pin Delay (tPD) 15 ns β€”
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) 5 V Β±10% (4.5 V to 5.5 V)
Technology CMOS EPROM, 1.0 um process CMOS, UV-erasable / OTP
Programmability UV-Erasable / OTP β€”
Package JLCC-28 (windowed ceramic) 28-pin PLCC (JEDEC S-PQCC-J28), 1.27 mm pitch
Operating Temperature 0C to +70C (commercial) 0 Β°C to +70 Β°C (commercial, "LC" suffix)
RoHS Status Non-compliant (contains Pb, ceramic-windowed package) Not RoHS compliant (legacy Altera product)
Device Family β€” MAX 5000
Product Terms β€” 320
I/O Pins β€” 16 bidirectional
Total Inputs β€” 24 (7 dedicated + 16 I/O used as input)
Propagation Delay (tPD) β€” 25 ns
Maximum Internal Frequency β€” 62.5 MHz
I/O Standard β€” 5 V CMOS
Mounting Type β€” Surface Mount, socket-compatible
Configuration Cell β€” Programmable interconnect array (PIA), OTP / UV-erasable

Datasheets & Resources

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