EPM5032LC-25 vs EPM5032JC-20 Comparison
Detailed side-by-side comparison of EPM5032LC-25 by Altera and EPM5032JC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032LC-25 | EPM5032JC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.20 | $9.75 |
| Device Family | MAX 5000 | β |
| Architecture | PAL-type EPLD (Erasable Programmable Logic Device) | PAL-type AND-OR array with PIA interconnect |
| Technology | CMOS, UV-erasable / OTP | β |
| Macrocells | 32 | 32 |
| Product Terms | 320 | β |
| Dedicated Inputs | 7 | 8 |
| I/O Pins | 16 bidirectional | β |
| Total Inputs | 24 (7 dedicated + 16 I/O used as input) | 24 |
| Propagation Delay (tPD) | 25 ns | 20 ns |
| Maximum Internal Frequency | 62.5 MHz | β |
| Supply Voltage (VCC) | 5 V Β±10% (4.5 V to 5.5 V) | β |
| I/O Standard | 5 V CMOS | β |
| Operating Temperature | 0 Β°C to +70 Β°C (commercial, "LC" suffix) | β |
| Package | 28-pin PLCC (JEDEC S-PQCC-J28), 1.27 mm pitch | 68-pin JLCC (windowed ceramic) |
| Mounting Type | Surface Mount, socket-compatible | β |
| Configuration Cell | Programmable interconnect array (PIA), OTP / UV-erasable | β |
| RoHS Status | Not RoHS compliant (legacy Altera product) | β |
| Product Type | β | UV-erasable Programmable Logic Device (PLD) |
| Family | β | MAX 5000 |
| Logic Array Blocks (LABs) | β | 1 |
| Product Terms (P-terms) | β | 320 |
| Maximum Clock Frequency | β | 62.5 MHz |
| Setup Time | β | 10 ns |
| I/O Lines | β | 16 (bidirectional) |
| Process Technology | β | CMOS |
| Erase Method | β | UV (12V VPP + ultraviolet exposure) |
| Programming Voltage (VPP) | β | 12 V |
| Lifecycle Status | β | Obsolete (legacy Altera MAX 5000) |