EPM5032LC-25 vs EPM5032LC-20 Comparison

Detailed side-by-side comparison of EPM5032LC-25 by Altera and EPM5032LC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM5032LC-20

EPM5032LC-20 - 32-Macrocell MAX 5000 CPLD, 20ns, LCC-28 | Altera

EPM5032LC-20 Obsolete

Specification Comparison

Parameter EPM5032LC-25 EPM5032LC-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.20 $8.40
Device Family MAX 5000 MAX 5000
Architecture PAL-type EPLD (Erasable Programmable Logic Device) β€”
Technology CMOS, UV-erasable / OTP β€”
Macrocells 32 32
Product Terms 320 β€”
Dedicated Inputs 7 7
I/O Pins 16 bidirectional β€”
Total Inputs 24 (7 dedicated + 16 I/O used as input) 24
Propagation Delay (tPD) 25 ns 20 ns
Maximum Internal Frequency 62.5 MHz β€”
Supply Voltage (VCC) 5 V Β±10% (4.5 V to 5.5 V) 5 V Β±5%
I/O Standard 5 V CMOS β€”
Operating Temperature 0 Β°C to +70 Β°C (commercial, "LC" suffix) 0 Β°C to +70 Β°C (commercial; -55 Β°C to +125 Β°C military per /883B variants)
Package 28-pin PLCC (JEDEC S-PQCC-J28), 1.27 mm pitch LCC-28 (Plastic Leaded Chip Carrier, J-lead)
Mounting Type Surface Mount, socket-compatible Surface Mount
Configuration Cell Programmable interconnect array (PIA), OTP / UV-erasable β€”
RoHS Status Not RoHS compliant (legacy Altera product) [DATA_NEEDED: RoHS status]
Product Type β€” EPLD / CPLD (One-Time Programmable / UV-Erasable)
Usable Gates β€” 600 gates
Logic Blocks (LABs) β€” 1
Speed Grade β€” -20 (20 ns pin-to-pin)
Maximum Frequency β€” 71.4 MHz
Bidirectional I/O Pins β€” 16
Output Functions β€” 16
Product Terms per Output β€” 16
Programmable Interconnect β€” Programmable Interconnect Array (PIA)
MSL Level β€” [DATA_NEEDED: MSL]

Datasheets & Resources

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