EPM5064JC-2 vs EPM5064JC Comparison
Detailed side-by-side comparison of EPM5064JC-2 by Altera and EPM5064JC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5064JC-2 | EPM5064JC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $23.10 | $7.10 |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | β |
| Propagation Delay (tPD) | 45 ns | β |
| Maximum Clock Frequency (fMAX) | 50 MHz | β |
| Usable Gates | 1250 | 1,250 (approx.) |
| Dedicated Inputs | 7 | β |
| I/O Pins | 28 | β |
| Interconnect | Programmable Interconnect Array (PIA) | β |
| Technology | CMOS, UV-erasable EPROM | β |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V (typical, 4.75 V - 5.25 V range) |
| Programming Method | UV-erase + EPROM programmer (not ISP) | β |
| Package | 28-pin CLCC (J-lead, ceramic, windowed) | 68-pin PLCC (JEDEC) |
| Operating Temperature | [DATA_NEEDED: commercial or industrial grade] | [DATA_NEEDED: operating temperature grade] |
| Compliance | RoHS status unknown (ceramic/J-lead windowed part, legacy product) | β |
| Device Type | β | EPLD (Erasable PLD) |
| Logic Array Inputs | β | 36 |
| Logic Array Outputs | β | 64 |
| Mounting Type | β | Surface Mount (socketed) |
| I/O Logic Level | β | TTL / CMOS compatible |
| Configuration Memory | β | EPROM (UV-erasable window or OTP) |
| Pin-to-Pin Delay (tPD) | β | [DATA_NEEDED: specific tPD grade value] |
| Maximum Frequency (fMAX) | β | [DATA_NEEDED: fCNT grade value] |
| RoHS Status | β | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |
| MSL Level | β | [DATA_NEEDED: MSL rating] |
| Programming Tool | β | Altera MAX+PLUS II / Quartus II (legacy device support) |