EPM5064JC vs EPM5032JC-20 Comparison

Detailed side-by-side comparison of EPM5064JC by Altera and EPM5032JC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5064JC EPM5032JC-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $7.10 $9.75
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable PLD) β€”
Macrocells 64 32
Usable Gates 1,250 (approx.) β€”
Logic Array Inputs 36 β€”
Logic Array Outputs 64 β€”
Package 68-pin PLCC (JEDEC) 68-pin JLCC (windowed ceramic)
Mounting Type Surface Mount (socketed) β€”
Supply Voltage (VCC) 5 V (typical, 4.75 V - 5.25 V range) β€”
I/O Logic Level TTL / CMOS compatible β€”
Configuration Memory EPROM (UV-erasable window or OTP) β€”
Operating Temperature [DATA_NEEDED: operating temperature grade] β€”
Pin-to-Pin Delay (tPD) [DATA_NEEDED: specific tPD grade value] β€”
Maximum Frequency (fMAX) [DATA_NEEDED: fCNT grade value] β€”
RoHS Status [DATA_NEEDED: RoHS compliance] β€”
Lead-Free [DATA_NEEDED: lead-free status] β€”
MSL Level [DATA_NEEDED: MSL rating] β€”
Programming Tool Altera MAX+PLUS II / Quartus II (legacy device support) β€”
Product Type β€” UV-erasable Programmable Logic Device (PLD)
Logic Array Blocks (LABs) β€” 1
Product Terms (P-terms) β€” 320
Propagation Delay (tPD) β€” 20 ns
Maximum Clock Frequency β€” 62.5 MHz
Setup Time β€” 10 ns
I/O Lines β€” 16 (bidirectional)
Dedicated Inputs β€” 8
Total Inputs β€” 24
Process Technology β€” CMOS
Erase Method β€” UV (12V VPP + ultraviolet exposure)
Programming Voltage (VPP) β€” 12 V
Architecture β€” PAL-type AND-OR array with PIA interconnect
Lifecycle Status β€” Obsolete (legacy Altera MAX 5000)

Datasheets & Resources

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