EPM5064JC vs EPM5064LI Comparison

Detailed side-by-side comparison of EPM5064JC by Altera and EPM5064LI by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5064JC EPM5064LI
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $7.10 $9.95
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable PLD) CPLD (Complex Programmable Logic Device)
Macrocells 64 64
Usable Gates 1,250 (approx.) β€”
Logic Array Inputs 36 β€”
Logic Array Outputs 64 β€”
Package 68-pin PLCC (JEDEC) β€”
Mounting Type Surface Mount (socketed) Surface Mount
Supply Voltage (VCC) 5 V (typical, 4.75 V - 5.25 V range) 4.5 V to 5.5 V
I/O Logic Level TTL / CMOS compatible β€”
Configuration Memory EPROM (UV-erasable window or OTP) UV-Erasable / OTP (EPROM-based)
Operating Temperature [DATA_NEEDED: operating temperature grade] β€”
Pin-to-Pin Delay (tPD) [DATA_NEEDED: specific tPD grade value] β€”
Maximum Frequency (fMAX) [DATA_NEEDED: fCNT grade value] β€”
RoHS Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: confirm RoHS status - legacy Altera part]
Lead-Free [DATA_NEEDED: lead-free status] β€”
MSL Level [DATA_NEEDED: MSL rating] β€”
Programming Tool Altera MAX+PLUS II / Quartus II (legacy device support) β€”
Logic Array Blocks (LABs) β€” 4
Number of Terminals β€” 44
Package Code β€” QCCJ (PLCC-44, J-bend)
Package Shape β€” Square
Operating Temperature Grade β€” Industrial
Maximum Clock Frequency β€” 33.3 MHz
Propagation Delay (tPD) β€” 55 ns (typical)
I/O Pins β€” 28 bidirectional
Dedicated Inputs β€” 7
Total User Inputs β€” 36
Process Technology β€” 1-micron EPIC CMOS
Latch-up Immunity β€” 500 mA typical at 125 C

Datasheets & Resources

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