EPM5064JC1 vs EPM5064JC Comparison

Detailed side-by-side comparison of EPM5064JC1 by Altera and EPM5064JC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5064JC1 EPM5064JC
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $1.05 $7.10
Family MAX 5000 MAX 5000
Device Type CPLD / EPLD (Erasable PLD) EPLD (Erasable PLD)
Macrocells 64 64
Logic Array Blocks (LABs) 4 β€”
Usable Gates 1.25K 1,250 (approx.)
Maximum Operating Frequency (fCNT) 62.5 MHz β€”
External Clock Input (max) 50 MHz β€”
I/O Pins 28 β€”
Dedicated Inputs 7 β€”
Total Inputs 36 (28 I/O + 7 dedicated + 1 clock) β€”
Operating Voltage (VCC) 5 V β€”
Program Type EPROM (one-time programmable, UV-erasable) β€”
Process Technology CMOS β€”
Package 44-pin PLCC (J-Lead) 68-pin PLCC (JEDEC)
Operating Temperature (JC suffix) 0Β°C to +70Β°C (commercial) β€”
Supply Current (ICC) [DATA_NEEDED: ICC maximum] β€”
RoHS Status unknown [DATA_NEEDED: RoHS compliance]
Lead-Free Status unknown β€”
Logic Array Inputs β€” 36
Logic Array Outputs β€” 64
Mounting Type β€” Surface Mount (socketed)
Supply Voltage (VCC) β€” 5 V (typical, 4.75 V - 5.25 V range)
I/O Logic Level β€” TTL / CMOS compatible
Configuration Memory β€” EPROM (UV-erasable window or OTP)
Operating Temperature β€” [DATA_NEEDED: operating temperature grade]
Pin-to-Pin Delay (tPD) β€” [DATA_NEEDED: specific tPD grade value]
Maximum Frequency (fMAX) β€” [DATA_NEEDED: fCNT grade value]
Lead-Free β€” [DATA_NEEDED: lead-free status]
MSL Level β€” [DATA_NEEDED: MSL rating]
Programming Tool β€” Altera MAX+PLUS II / Quartus II (legacy device support)

Datasheets & Resources

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