EPM5128GC-1 vs EPM5128GC-2 Comparison
Detailed side-by-side comparison of EPM5128GC-1 by Altera and EPM5128GC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5128GC-1 | EPM5128GC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $18.95 | $8.95 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-erasable CMOS CPLD | β |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | β |
| Dedicated Inputs | 7 | β |
| Maximum User I/O Pins | 52 | β |
| Nominal Supply Voltage | 5 V | β |
| Supply Voltage Range | 4.75 V to 5.25 V | β |
| Maximum Operating Frequency | 62.5 MHz | 50 MHz |
| Propagation Delay (tPD) | 16 ns (typical, -1 speed grade) | Approx. 25 ns (typical, -2 speed grade) |
| Package | PGA-96+ (Pin Grid Array, ceramic windowed) | β |
| Technology | CMOS, UV-erasable EPROM | β |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) |
| IOL / IOH | 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec]) | β |
| Security Bit | Programmable, prevents readback | β |
| Programming Method | UV erase + EPROM program (or device programmer) | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy] | β |
| Logic Elements / Gates | β | 2,500 usable gates |
| Number of Usable Gates | β | 2,500 |
| Supply Voltage (VCC) | β | 5 V (nominal) |
| Package Type | β | 68-pin PGA (Pin Grid Array) |
| Package Code (per Partstack) | β | WPGA |
| Number of Terminals | β | 68 |
| Programming Technology | β | UV-erasable EPROM |
| Grade (per Partstack) | β | COMMERCIAL |
| Terminal Form | β | PIN/PEG |
| Configuration Memory | β | Non-volatile, one-time programmable (erasable via UV) |