EPM5128GC-1 vs EPM5128GC2 Comparison

Detailed side-by-side comparison of EPM5128GC-1 by Altera and EPM5128GC2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5128GC-1 EPM5128GC2
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $18.95 $54.00
Family MAX 5000 MAX 5000
Device Type UV-erasable CMOS CPLD EPLD (Erasable Programmable Logic Device)
Macrocells 128 β€”
Usable Gates 2,500 2.5K
Dedicated Inputs 7 16
Maximum User I/O Pins 52 β€”
Nominal Supply Voltage 5 V β€”
Supply Voltage Range 4.75 V to 5.25 V β€”
Maximum Operating Frequency 62.5 MHz β€”
Propagation Delay (tPD) 16 ns (typical, -1 speed grade) β€”
Package PGA-96+ (Pin Grid Array, ceramic windowed) Ceramic PGA (GC, windowed)
Technology CMOS, UV-erasable EPROM β€”
Operating Temperature -40C to +85C (industrial) [DATA_NEEDED: operating temperature range]
IOL / IOH 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec]) β€”
Security Bit Programmable, prevents readback β€”
Programming Method UV erase + EPROM program (or device programmer) β€”
MSL Level [DATA_NEEDED: MSL level] β€”
RoHS Status [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy] [DATA_NEEDED: RoHS status]
Macro Cells β€” 128
Logic Array Blocks (LABs) β€” 8 (16 macro cells each)
Maximum Internal Frequency β€” 50 MHz
Supply Voltage VCC β€” 5 V
I/O Pins β€” 64
Programmable Flip-Flop Modes β€” D / T / JK / SR (selectable)
Architecture β€” AND/OR plane + programmable macro cell + PIA
Process Technology β€” CMOS EPROM
Reprogrammability β€” UV-erasable (windowed ceramic package)
Configuration Memory β€” On-chip EPROM (no external boot device)
Pin Count β€” [DATA_NEEDED: total PGA pin count]

Datasheets & Resources

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