EPM5128GC-1 vs EPM5128JC Comparison
Detailed side-by-side comparison of EPM5128GC-1 by Altera and EPM5128JC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5128GC-1 | EPM5128JC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $18.95 | $9.75 |
| Family | MAX 5000 | β |
| Device Type | UV-erasable CMOS CPLD | EPLD / CPLD |
| Macrocells | 128 | β |
| Usable Gates | 2,500 | β |
| Dedicated Inputs | 7 | 8 |
| Maximum User I/O Pins | 52 | β |
| Nominal Supply Voltage | 5 V | β |
| Supply Voltage Range | 4.75 V to 5.25 V | β |
| Maximum Operating Frequency | 62.5 MHz | β |
| Propagation Delay (tPD) | 16 ns (typical, -1 speed grade) | 35 ns |
| Package | PGA-96+ (Pin Grid Array, ceramic windowed) | β |
| Technology | CMOS, UV-erasable EPROM | β |
| Operating Temperature | -40C to +85C (industrial) | Commercial 0C to +70C |
| IOL / IOH | 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec]) | β |
| Security Bit | Programmable, prevents readback | β |
| Programming Method | UV erase + EPROM program (or device programmer) | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy] | [DATA_NEEDED: RoHS status - legacy part] |
| Product Family | β | MAX 5000 |
| Macrocell Count | β | 128 |
| Logic Elements | β | Programmable AND/OR/XOR array |
| Supply Voltage (VCC) | β | 5 V (typical) |
| Number of Pins | β | 68 |
| Package Type | β | PLCC-68 (JLCC) ceramic, J-leaded |
| User I/O Pins | β | [DATA_NEEDED: user I/O pin count] |
| Configuration Memory | β | UV-erasable EPROM (windowed package) |
| Programming Interface | β | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Mounting Type | β | Surface Mount (PLCC socket or solder) |
| Boundary Scan | β | JTAG IEEE 1149.1 (family feature) |
| Process Technology | β | CMOS EPROM |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |