EPM5128GC-2 vs EPM5128JC-2 Comparison

Detailed side-by-side comparison of EPM5128GC-2 by Altera and EPM5128JC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5128GC-2 EPM5128JC-2
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.95 $21.75
Family MAX 5000 MAX 5000
Logic Elements / Gates 2,500 usable gates β€”
Macrocells 128 128
Number of Usable Gates 2,500 β€”
Maximum Operating Frequency 50 MHz β€”
Propagation Delay (tPD) Approx. 25 ns (typical, -2 speed grade) 45 ns (max)
Supply Voltage (VCC) 5 V (nominal) β€”
Package Type 68-pin PGA (Pin Grid Array) β€”
Package Code (per Partstack) WPGA β€”
Number of Terminals 68 β€”
Programming Technology UV-erasable EPROM β€”
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
Grade (per Partstack) COMMERCIAL β€”
Terminal Form PIN/PEG β€”
Configuration Memory Non-volatile, one-time programmable (erasable via UV) β€”
Device Type β€” UV-Erasable Programmable Logic Device (PLD)
Dedicated Inputs β€” 7
Maximum Counter Frequency (fCNT) β€” 50 MHz
Input Setup Time (tSU) β€” 7.5 ns
Output Drive Current (IOH/IOL) β€” 12 mA DC
Process Technology β€” CMOS
Package β€” 68-pin CQCC (Ceramic Quad Flat Pack), windowed
Mounting Type β€” Surface Mount
Supply Voltage β€” 5 V (nominal)
Program/Erase Method β€” UV (ceramic window)
Erase/Program Cycles β€” [DATA_NEEDED: minimum erase/program cycles]
RoHS Status β€” Non-compliant (ceramic windowed package contains lead-bearing solder)
Logic Family β€” TTL-compatible I/O

Datasheets & Resources

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