EPM5128JC-1 vs EPM5128GC-2 Comparison

Detailed side-by-side comparison of EPM5128JC-1 by Altera and EPM5128GC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM5128JC-1

EPM5128JC-1 - 128-Macrocell MAX 5000 CPLD 40ns | Altera

EPM5128JC-1 Obsolete
Altera
EPM5128GC-2

EPM5128GC-2 - 128-Macrocell MAX 5000 CPLD, 50MHz, 5V | Altera

EPM5128GC-2 Obsolete

Specification Comparison

Parameter EPM5128JC-1 EPM5128GC-2
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $24.95 $8.95
Family MAX 5000 MAX 5000
Device Type Erasable Programmable Logic Device (EPLD/CPLD) β€”
Macrocells 128 128
Usable Gates 2,500 β€”
Logic Array Blocks (LABs) [DATA_NEEDED: LAB count] β€”
Maximum Operating Frequency 62.5 MHz 50 MHz
Pin-to-Pin Propagation Delay (tPD) 40 ns β€”
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (nominal)
Technology CMOS, UV-erasable EPROM β€”
Package 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier) β€”
Mounting Type Surface Mount β€”
Operating Temperature [DATA_NEEDED: temperature grade] 0C to +70C (commercial)
Programming Interface JTAG / Altera dedicated programmer β€”
Configuration Memory Non-volatile EPROM (UV-erasable) Non-volatile, one-time programmable (erasable via UV)
RoHS Status non_compliant (ceramic windowed package) β€”
Lifecycle Status Obsolete - last-time-buy inventory only β€”
Logic Elements / Gates β€” 2,500 usable gates
Number of Usable Gates β€” 2,500
Propagation Delay (tPD) β€” Approx. 25 ns (typical, -2 speed grade)
Package Type β€” 68-pin PGA (Pin Grid Array)
Package Code (per Partstack) β€” WPGA
Number of Terminals β€” 68
Programming Technology β€” UV-erasable EPROM
Grade (per Partstack) β€” COMMERCIAL
Terminal Form β€” PIN/PEG

Datasheets & Resources

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