EPM5128JC-2 vs EPM5128JC Comparison

Detailed side-by-side comparison of EPM5128JC-2 by Altera and EPM5128JC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM5128JC-2

EPM5128JC-2 - 128-Macrocell UV PLD, 45ns, CQCC-68 | Altera

EPM5128JC-2 Obsolete

Specification Comparison

Parameter EPM5128JC-2 EPM5128JC
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $21.75 $9.75
Family MAX 5000 β€”
Device Type UV-Erasable Programmable Logic Device (PLD) EPLD / CPLD
Macrocells 128 β€”
Dedicated Inputs 7 8
Propagation Delay (tPD) 45 ns (max) 35 ns
Maximum Counter Frequency (fCNT) 50 MHz β€”
Input Setup Time (tSU) 7.5 ns β€”
Output Drive Current (IOH/IOL) 12 mA DC β€”
Process Technology CMOS CMOS EPROM
Package 68-pin CQCC (Ceramic Quad Flat Pack), windowed β€”
Mounting Type Surface Mount Surface Mount (PLCC socket or solder)
Operating Temperature [DATA_NEEDED: operating temperature range] Commercial 0C to +70C
Supply Voltage 5 V (nominal) β€”
Program/Erase Method UV (ceramic window) β€”
Erase/Program Cycles [DATA_NEEDED: minimum erase/program cycles] β€”
RoHS Status Non-compliant (ceramic windowed package contains lead-bearing solder) [DATA_NEEDED: RoHS status - legacy part]
Logic Family TTL-compatible I/O β€”
Product Family β€” MAX 5000
Macrocell Count β€” 128
Logic Elements β€” Programmable AND/OR/XOR array
Supply Voltage (VCC) β€” 5 V (typical)
Number of Pins β€” 68
Package Type β€” PLCC-68 (JLCC) ceramic, J-leaded
User I/O Pins β€” [DATA_NEEDED: user I/O pin count]
Configuration Memory β€” UV-erasable EPROM (windowed package)
Programming Interface β€” Altera MAX+PLUS II / A+PLUS / legacy programmer
Boundary Scan β€” JTAG IEEE 1149.1 (family feature)
Lead-Free β€” [DATA_NEEDED: lead-free status]

Datasheets & Resources

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