EPM5128JC-2 vs EPM5128LC2 Comparison
Detailed side-by-side comparison of EPM5128JC-2 by Altera and EPM5128LC2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5128LC2
EPM5128LC2 - 128-Macrocell MAX 5000 CPLD, 45ns, 5V | Altera
EPM5128LC2 β Last Time BuySpecification Comparison
| Parameter | EPM5128JC-2 | EPM5128LC2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $21.75 | $22.40 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable Programmable Logic Device (PLD) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | 128 |
| Dedicated Inputs | 7 | β |
| Propagation Delay (tPD) | 45 ns (max) | 45 ns |
| Maximum Counter Frequency (fCNT) | 50 MHz | β |
| Input Setup Time (tSU) | 7.5 ns | β |
| Output Drive Current (IOH/IOL) | 12 mA DC | β |
| Process Technology | CMOS | CMOS EPROM |
| Package | 68-pin CQCC (Ceramic Quad Flat Pack), windowed | PGA (Pin Grid Array, ceramic) |
| Mounting Type | Surface Mount | Through-Hole / Socketed |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (extended commercial) |
| Supply Voltage | 5 V (nominal) | β |
| Program/Erase Method | UV (ceramic window) | β |
| Erase/Program Cycles | [DATA_NEEDED: minimum erase/program cycles] | β |
| RoHS Status | Non-compliant (ceramic windowed package contains lead-bearing solder) | [DATA_NEEDED: RoHS status] |
| Logic Family | TTL-compatible I/O | β |
| Logic Array Blocks (LABs) | β | 8 |
| Interconnect | β | Programmable Interconnect Array (PIA) |
| Global Clock Inputs | β | 1 dedicated |
| Supply Voltage (VCC) | β | 5 V |
| Configuration Memory | β | On-chip EPROM (non-volatile) |
| Boundary Scan | β | JTAG / IEEE 1149.1 |