EPM5128JC-2 vs EPM5130JC-1 Comparison
Detailed side-by-side comparison of EPM5128JC-2 by Altera and EPM5130JC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5130JC-1
EPM5130JC-1 - 2.5K Gate 128-Macrocell CPLD | Altera/Intel MAX 5000
EPM5130JC-1 ObsoleteSpecification Comparison
| Parameter | EPM5128JC-2 | EPM5130JC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $21.75 | $9.25 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable Programmable Logic Device (PLD) | β |
| Macrocells | 128 | 128 |
| Dedicated Inputs | 7 | 19 |
| Propagation Delay (tPD) | 45 ns (max) | 40 ns |
| Maximum Counter Frequency (fCNT) | 50 MHz | β |
| Input Setup Time (tSU) | 7.5 ns | β |
| Output Drive Current (IOH/IOL) | 12 mA DC | β |
| Process Technology | CMOS | CMOS |
| Package | 68-pin CQCC (Ceramic Quad Flat Pack), windowed | 84-pin PLCC (J-lead) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Supply Voltage | 5 V (nominal) | β |
| Program/Erase Method | UV (ceramic window) | β |
| Erase/Program Cycles | [DATA_NEEDED: minimum erase/program cycles] | β |
| RoHS Status | Non-compliant (ceramic windowed package contains lead-bearing solder) | [DATA_NEEDED: RoHS compliance] |
| Logic Family | TTL-compatible I/O | β |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Usable Gates | β | 2,500 gates |
| Logic Array Blocks (LABs) | β | 8 |
| Maximum Operating Frequency | β | 62.5 MHz |
| Supply Voltage (VCC) | β | 5 V |
| I/O Pins | β | 80 |
| Programming Technology | β | UV-erasable EPROM (quartz window) |
| External Clock Pins | β | 1 global clock |