EPM5128JC vs EPM5064JC Comparison

Detailed side-by-side comparison of EPM5128JC by Altera and EPM5064JC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5128JC EPM5064JC
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.75 $7.10
Product Family MAX 5000 β€”
Device Type EPLD / CPLD EPLD (Erasable PLD)
Macrocell Count 128 β€”
Propagation Delay (tPD) 35 ns β€”
Logic Elements Programmable AND/OR/XOR array β€”
Supply Voltage (VCC) 5 V (typical) 5 V (typical, 4.75 V - 5.25 V range)
Number of Pins 68 β€”
Package Type PLCC-68 (JLCC) ceramic, J-leaded β€”
Dedicated Inputs 8 β€”
User I/O Pins [DATA_NEEDED: user I/O pin count] β€”
Configuration Memory UV-erasable EPROM (windowed package) EPROM (UV-erasable window or OTP)
Programming Interface Altera MAX+PLUS II / A+PLUS / legacy programmer β€”
Operating Temperature Commercial 0C to +70C [DATA_NEEDED: operating temperature grade]
Mounting Type Surface Mount (PLCC socket or solder) Surface Mount (socketed)
Boundary Scan JTAG IEEE 1149.1 (family feature) β€”
Process Technology CMOS EPROM β€”
RoHS Status [DATA_NEEDED: RoHS status - legacy part] [DATA_NEEDED: RoHS compliance]
Lead-Free [DATA_NEEDED: lead-free status] [DATA_NEEDED: lead-free status]
Family β€” MAX 5000
Macrocells β€” 64
Usable Gates β€” 1,250 (approx.)
Logic Array Inputs β€” 36
Logic Array Outputs β€” 64
Package β€” 68-pin PLCC (JEDEC)
I/O Logic Level β€” TTL / CMOS compatible
Pin-to-Pin Delay (tPD) β€” [DATA_NEEDED: specific tPD grade value]
Maximum Frequency (fMAX) β€” [DATA_NEEDED: fCNT grade value]
MSL Level β€” [DATA_NEEDED: MSL rating]
Programming Tool β€” Altera MAX+PLUS II / Quartus II (legacy device support)

Datasheets & Resources

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