EPM5128JC vs EPM5128GM883B Comparison
Detailed side-by-side comparison of EPM5128JC by Altera and EPM5128GM883B by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5128JC | EPM5128GM883B |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $159.25 |
| Product Family | MAX 5000 | β |
| Device Type | EPLD / CPLD | UV EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | 128 | β |
| Propagation Delay (tPD) | 35 ns | β |
| Logic Elements | Programmable AND/OR/XOR array | β |
| Supply Voltage (VCC) | 5 V (typical) | β |
| Number of Pins | 68 | β |
| Package Type | PLCC-68 (JLCC) ceramic, J-leaded | β |
| Dedicated Inputs | 8 | 7 |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | 52 |
| Configuration Memory | UV-erasable EPROM (windowed package) | UV-erasable EPROM |
| Programming Interface | Altera MAX+PLUS II / A+PLUS / legacy programmer | β |
| Operating Temperature | Commercial 0C to +70C | -55C to +125C (military) |
| Mounting Type | Surface Mount (PLCC socket or solder) | β |
| Boundary Scan | JTAG IEEE 1149.1 (family feature) | β |
| Process Technology | CMOS EPROM | β |
| RoHS Status | [DATA_NEEDED: RoHS status - legacy part] | β |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Family | β | MAX 5000 |
| Macrocells | β | 128 |
| Logic Array Blocks (LABs) | β | 8 |
| Propagation Delay (tpd) | β | 55 ns |
| External Clock Inputs | β | 1 |
| Technology | β | CMOS |
| Interconnect | β | Programmable Interconnect Array (PIA) |
| Package | β | PGA-883 (ceramic pin grid array) |
| Qualification | β | MIL-STD-883 Class B (suffix 883B) |
| Program/Erase Method | β | UV-erasable |