EPM5128JI vs EPM5128JC Comparison
Detailed side-by-side comparison of EPM5128JI by Intel and EPM5128JC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5128JI | EPM5128JC |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $23.95 | $9.75 |
| Device Family | MAX 5000 | β |
| Device Type | UV-erasable programmable logic device (PLD) | EPLD / CPLD |
| Macrocells | 128 | β |
| Propagation Delay (tPD) | 55 ns (typical) | 35 ns |
| Maximum Internal Frequency | 40 MHz | β |
| Process Technology | CMOS | CMOS EPROM |
| Programmable Technology | UV-erasable EPROM cell | β |
| Package | 68-terminal ceramic CQCC, windowed, J-leads | β |
| Operating Temperature Grade | Industrial ("I" suffix) | β |
| Programming | Altera MAX+plus II compatible programmer + UV eraser | β |
| RoHS Status | Non-compliant (ceramic hermetic package) | [DATA_NEEDED: RoHS status - legacy part] |
| Lead Finish | Tin-lead (SnPb) over nickel | β |
| Mounting Type | Surface Mount (J-lead CQCC) | Surface Mount (PLCC socket or solder) |
| Logic Blocks | [DATA_NEEDED: number of LABs / logic array blocks] | β |
| User I/O Pins | [DATA_NEEDED: pin count of user I/Os] | [DATA_NEEDED: user I/O pin count] |
| Supply Voltage | [DATA_NEEDED: VCC range] | β |
| Standby Current | [DATA_NEEDED: ICCSB] | β |
| Product Family | β | MAX 5000 |
| Macrocell Count | β | 128 |
| Logic Elements | β | Programmable AND/OR/XOR array |
| Supply Voltage (VCC) | β | 5 V (typical) |
| Number of Pins | β | 68 |
| Package Type | β | PLCC-68 (JLCC) ceramic, J-leaded |
| Dedicated Inputs | β | 8 |
| Configuration Memory | β | UV-erasable EPROM (windowed package) |
| Programming Interface | β | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Operating Temperature | β | Commercial 0C to +70C |
| Boundary Scan | β | JTAG IEEE 1149.1 (family feature) |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |