EPM5128LC-1 vs EPM5128JC Comparison
Detailed side-by-side comparison of EPM5128LC-1 by Altera and EPM5128JC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5128LC-1
EPM5128LC-1 - 128-Macrocell MAX 5000 CPLD | Altera | 5V 68-Pin PLCC
EPM5128LC-1 ObsoleteSpecification Comparison
| Parameter | EPM5128LC-1 | EPM5128JC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.20 | $9.75 |
| Family | MAX 5000 | β |
| Logic Elements / Macrocells | 128 macrocells | β |
| Number of Usable Gates | [DATA_NEEDED: usable gates] | β |
| Dedicated Inputs | 7 | 8 |
| Bidirectional I/O Pins | 52 | β |
| Total User I/O | 60 (max) | β |
| Propagation Delay (tpd) | 30 ns | β |
| Supply Voltage (VCC) | 5 V (Β±10%) | 5 V (typical) |
| Process Technology | CMOS EPROM, UV-erasable | CMOS EPROM |
| Programmability | UV-erasable / OTP (windowed package) | β |
| Package Type | 68-pin J-lead ceramic chip carrier (PLCC windowed) | PLCC-68 (JLCC) ceramic, J-leaded |
| Operating Temperature | 0C to +70C (commercial) | Commercial 0C to +70C |
| JTAG Support | IEEE 1149.1 boundary-scan | β |
| Mounting Type | Surface Mount (J-lead PLCC socket compatible) | Surface Mount (PLCC socket or solder) |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - legacy part] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Product Family | β | MAX 5000 |
| Device Type | β | EPLD / CPLD |
| Macrocell Count | β | 128 |
| Propagation Delay (tPD) | β | 35 ns |
| Logic Elements | β | Programmable AND/OR/XOR array |
| Number of Pins | β | 68 |
| User I/O Pins | β | [DATA_NEEDED: user I/O pin count] |
| Configuration Memory | β | UV-erasable EPROM (windowed package) |
| Programming Interface | β | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Boundary Scan | β | JTAG IEEE 1149.1 (family feature) |