EPM5128LC-1 vs EPM5128JC-1 Comparison

Detailed side-by-side comparison of EPM5128LC-1 by Altera and EPM5128JC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM5128JC-1

EPM5128JC-1 - 128-Macrocell MAX 5000 CPLD 40ns | Altera

EPM5128JC-1 Obsolete

Specification Comparison

Parameter EPM5128LC-1 EPM5128JC-1
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.20 $24.95
Family MAX 5000 MAX 5000
Logic Elements / Macrocells 128 macrocells β€”
Number of Usable Gates [DATA_NEEDED: usable gates] β€”
Dedicated Inputs 7 β€”
Bidirectional I/O Pins 52 β€”
Total User I/O 60 (max) β€”
Propagation Delay (tpd) 30 ns β€”
Supply Voltage (VCC) 5 V (Β±10%) 4.75 V to 5.25 V (5 V nominal)
Process Technology CMOS EPROM, UV-erasable β€”
Programmability UV-erasable / OTP (windowed package) β€”
Package Type 68-pin J-lead ceramic chip carrier (PLCC windowed) β€”
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: temperature grade]
JTAG Support IEEE 1149.1 boundary-scan β€”
Mounting Type Surface Mount (J-lead PLCC socket compatible) Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] non_compliant (ceramic windowed package)
Lead-Free [DATA_NEEDED: lead-free status] β€”
Device Type β€” Erasable Programmable Logic Device (EPLD/CPLD)
Macrocells β€” 128
Usable Gates β€” 2,500
Logic Array Blocks (LABs) β€” [DATA_NEEDED: LAB count]
Maximum Operating Frequency β€” 62.5 MHz
Pin-to-Pin Propagation Delay (tPD) β€” 40 ns
Technology β€” CMOS, UV-erasable EPROM
Package β€” 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier)
Programming Interface β€” JTAG / Altera dedicated programmer
Configuration Memory β€” Non-volatile EPROM (UV-erasable)
Lifecycle Status β€” Obsolete - last-time-buy inventory only

Datasheets & Resources

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