EPM5128LC-1 vs EPM5128LC2 Comparison

Detailed side-by-side comparison of EPM5128LC-1 by Altera and EPM5128LC2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM5128LC2

EPM5128LC2 - 128-Macrocell MAX 5000 CPLD, 45ns, 5V | Altera

EPM5128LC2 ⚠ Last Time Buy

Specification Comparison

Parameter EPM5128LC-1 EPM5128LC2
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $8.20 $22.40
Family MAX 5000 MAX 5000
Logic Elements / Macrocells 128 macrocells β€”
Number of Usable Gates [DATA_NEEDED: usable gates] β€”
Dedicated Inputs 7 β€”
Bidirectional I/O Pins 52 β€”
Total User I/O 60 (max) β€”
Propagation Delay (tpd) 30 ns β€”
Supply Voltage (VCC) 5 V (Β±10%) 5 V
Process Technology CMOS EPROM, UV-erasable CMOS EPROM
Programmability UV-erasable / OTP (windowed package) β€”
Package Type 68-pin J-lead ceramic chip carrier (PLCC windowed) β€”
Operating Temperature 0C to +70C (commercial) -40 C to +85 C (extended commercial)
JTAG Support IEEE 1149.1 boundary-scan β€”
Mounting Type Surface Mount (J-lead PLCC socket compatible) Through-Hole / Socketed
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
Macrocells β€” 128
Logic Array Blocks (LABs) β€” 8
Interconnect β€” Programmable Interconnect Array (PIA)
Global Clock Inputs β€” 1 dedicated
Propagation Delay (tPD) β€” 45 ns
Configuration Memory β€” On-chip EPROM (non-volatile)
Boundary Scan β€” JTAG / IEEE 1149.1
Package β€” PGA (Pin Grid Array, ceramic)

Datasheets & Resources

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