EPM5128LC-1 vs EPM5130GI Comparison
Detailed side-by-side comparison of EPM5128LC-1 by Altera and EPM5130GI by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5128LC-1 | EPM5130GI |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.20 | $16.20 |
| Family | MAX 5000 | β |
| Logic Elements / Macrocells | 128 macrocells | β |
| Number of Usable Gates | [DATA_NEEDED: usable gates] | β |
| Dedicated Inputs | 7 | 19 |
| Bidirectional I/O Pins | 52 | β |
| Total User I/O | 60 (max) | β |
| Propagation Delay (tpd) | 30 ns | β |
| Supply Voltage (VCC) | 5 V (Β±10%) | β |
| Process Technology | CMOS EPROM, UV-erasable | CMOS |
| Programmability | UV-erasable / OTP (windowed package) | β |
| Package Type | 68-pin J-lead ceramic chip carrier (PLCC windowed) | β |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial) |
| JTAG Support | IEEE 1149.1 boundary-scan | β |
| Mounting Type | Surface Mount (J-lead PLCC socket compatible) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Device Family | β | MAX 5000 |
| Architecture | β | EPLD (Erasable Programmable Logic Device), UV-erasable |
| Macrocells | β | 128 |
| Logic Array Blocks (LABs) | β | 8 |
| Interconnect | β | Programmable Interconnect Array (PIA) |
| Total Inputs | β | 68 |
| I/O Pins | β | 48 |
| Propagation Delay (tPD) | β | 55 ns |
| Maximum Clock Frequency (fMAX) | β | 33.3 MHz |
| External Clock Pins | β | 1 |
| Supply Voltage | β | 5 V |
| Package | β | Ceramic Pin Grid Array (PGA), windowed |
| Programming Method | β | UV erasure + EPROM programming |