EPM5130JC-1 vs EPM5128JC Comparison
Detailed side-by-side comparison of EPM5130JC-1 by Altera and EPM5128JC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5130JC-1
EPM5130JC-1 - 2.5K Gate 128-Macrocell CPLD | Altera/Intel MAX 5000
EPM5130JC-1 ObsoleteSpecification Comparison
| Parameter | EPM5130JC-1 | EPM5128JC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.25 | $9.75 |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Family | MAX 5000 | β |
| Usable Gates | 2,500 gates | β |
| Macrocells | 128 | β |
| Logic Array Blocks (LABs) | 8 | β |
| Maximum Operating Frequency | 62.5 MHz | β |
| Propagation Delay (tPD) | 40 ns | 35 ns |
| Supply Voltage (VCC) | 5 V | 5 V (typical) |
| Dedicated Inputs | 19 | 8 |
| I/O Pins | 80 | β |
| Package | 84-pin PLCC (J-lead) | β |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket or solder) |
| Programming Technology | UV-erasable EPROM (quartz window) | β |
| Process Technology | CMOS | CMOS EPROM |
| Operating Temperature | 0C to +70C (commercial) | Commercial 0C to +70C |
| External Clock Pins | 1 global clock | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status - legacy part] |
| Product Family | β | MAX 5000 |
| Device Type | β | EPLD / CPLD |
| Macrocell Count | β | 128 |
| Logic Elements | β | Programmable AND/OR/XOR array |
| Number of Pins | β | 68 |
| Package Type | β | PLCC-68 (JLCC) ceramic, J-leaded |
| User I/O Pins | β | [DATA_NEEDED: user I/O pin count] |
| Configuration Memory | β | UV-erasable EPROM (windowed package) |
| Programming Interface | β | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Boundary Scan | β | JTAG IEEE 1149.1 (family feature) |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |