EPM5130JC-1 vs EPM5130WC-2 Comparison
Detailed side-by-side comparison of EPM5130JC-1 by Altera and EPM5130WC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5130JC-1
EPM5130JC-1 - 2.5K Gate 128-Macrocell CPLD | Altera/Intel MAX 5000
EPM5130JC-1 ObsoleteAltera
EPM5130WC-2
EPM5130WC-2 - 128-Macrocell UV PLD MAX 5000 | Altera CQFP-100
EPM5130WC-2 ObsoleteSpecification Comparison
| Parameter | EPM5130JC-1 | EPM5130WC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.25 | $62.00 |
| Product Type | CPLD (Complex Programmable Logic Device) | UV-Erasable PLD (CPLD) |
| Family | MAX 5000 | β |
| Usable Gates | 2,500 gates | β |
| Macrocells | 128 | β |
| Logic Array Blocks (LABs) | 8 | β |
| Maximum Operating Frequency | 62.5 MHz | β |
| Propagation Delay (tPD) | 40 ns | 45 ns |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| Dedicated Inputs | 19 | 19 |
| I/O Pins | 80 | β |
| Package | 84-pin PLCC (J-lead) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Technology | UV-erasable EPROM (quartz window) | β |
| Process Technology | CMOS | CMOS |
| Operating Temperature | 0C to +70C (commercial) | 0 Β°C to 70 Β°C (Commercial) |
| External Clock Pins | 1 global clock | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Device Family | β | MAX 5000 |
| Macrocell Count | β | 128 |
| User I/O Lines | β | 48 |
| Total Inputs (I/O + dedicated) | β | 68 |
| Package Type | β | 100-terminal Ceramic CQFP (R-CQFP-G100), windowed, gull-wing |
| Terminal Pitch | β | 0.650 mm |
| Configuration Memory | β | UV-erasable CMOS EEPROM cells |
| Speed Grade | β | -2 (45 ns) |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |
| Logic Elements | β | AND/OR array with programmable macrocell register |