EPM5130JI vs EPM5130GI Comparison
Detailed side-by-side comparison of EPM5130JI by Altera and EPM5130GI by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5130JI | EPM5130GI |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $16.20 |
| Family | MAX 5000 | β |
| Device Type | UV-Erasable EPLD (CMOS EPROM) | β |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 8 |
| Maximum Clock Frequency | 33.3 MHz | β |
| Propagation Delay (tPD) | 55 ns | 55 ns |
| External Clock Inputs | 1 (shared input/clock) | β |
| Interconnect | Programmable Interconnect Array (PIA) | Programmable Interconnect Array (PIA) |
| Process Technology | 0.75 micron CMOS EPROM | CMOS |
| Supply Voltage | 5 V (typical) | 5 V |
| Input Logic Standard | TTL-compatible | β |
| Package Type | Ceramic J-Leaded Chip Carrier (JLCC) with UV window | β |
| Operating Temperature | Commercial (0C to +70C) | -40C to +85C (industrial) |
| Program/Erase Method | UV erasure through quartz window | β |
| RoHS Status | Non-compliant (contains Pb in ceramic package) | [DATA_NEEDED: RoHS status] |
| Lifecycle | Obsolete - EOL by Altera/Intel | β |
| Device Family | β | MAX 5000 |
| Architecture | β | EPLD (Erasable Programmable Logic Device), UV-erasable |
| Dedicated Inputs | β | 19 |
| Total Inputs | β | 68 |
| I/O Pins | β | 48 |
| Maximum Clock Frequency (fMAX) | β | 33.3 MHz |
| External Clock Pins | β | 1 |
| Package | β | Ceramic Pin Grid Array (PGA), windowed |
| Programming Method | β | UV erasure + EPROM programming |