EPM5130JI vs EPM5130JC-1 Comparison
Detailed side-by-side comparison of EPM5130JI by Altera and EPM5130JC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5130JC-1
EPM5130JC-1 - 2.5K Gate 128-Macrocell CPLD | Altera/Intel MAX 5000
EPM5130JC-1 ObsoleteSpecification Comparison
| Parameter | EPM5130JI | EPM5130JC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $9.25 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable EPLD (CMOS EPROM) | β |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 8 |
| Maximum Clock Frequency | 33.3 MHz | β |
| Propagation Delay (tPD) | 55 ns | 40 ns |
| External Clock Inputs | 1 (shared input/clock) | β |
| Interconnect | Programmable Interconnect Array (PIA) | β |
| Process Technology | 0.75 micron CMOS EPROM | CMOS |
| Supply Voltage | 5 V (typical) | β |
| Input Logic Standard | TTL-compatible | β |
| Package Type | Ceramic J-Leaded Chip Carrier (JLCC) with UV window | β |
| Operating Temperature | Commercial (0C to +70C) | 0C to +70C (commercial) |
| Program/Erase Method | UV erasure through quartz window | β |
| RoHS Status | Non-compliant (contains Pb in ceramic package) | [DATA_NEEDED: RoHS compliance] |
| Lifecycle | Obsolete - EOL by Altera/Intel | β |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Usable Gates | β | 2,500 gates |
| Maximum Operating Frequency | β | 62.5 MHz |
| Supply Voltage (VCC) | β | 5 V |
| Dedicated Inputs | β | 19 |
| I/O Pins | β | 80 |
| Package | β | 84-pin PLCC (J-lead) |
| Mounting Type | β | Surface Mount |
| Programming Technology | β | UV-erasable EPROM (quartz window) |
| External Clock Pins | β | 1 global clock |