EPM5130LC vs EPM5128LC2 Comparison

Detailed side-by-side comparison of EPM5130LC by Altera and EPM5128LC2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM5128LC2 EPM5128LC2 - 128-Macrocell MAX 5000 CPLD, 45ns, 5V | Altera

EPM5128LC2 - 128-Macrocell MAX 5000 CPLD, 45ns, 5V | Altera

EPM5128LC2 ⚠ Last Time Buy

Specification Comparison

Parameter EPM5130LC EPM5128LC2
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $15.60 $22.40
Series MAX 5000 β€”
Family MAX 5000 (EPM51xx) MAX 5000
Macrocells 128 128
Logic Array Blocks (LABs) 8 8
User I/O Pins 48 β€”
Total Inputs (Dedicated + I/O) 68 β€”
Dedicated Inputs 19 β€”
Propagation Delay (tPD) 55 ns 45 ns
Maximum Internal Clock Frequency 50 MHz β€”
Global Clock Inputs 1 1 dedicated
Configuration Technology UV-Erasable / OTP EPROM β€”
Process Technology CMOS (0.7 um EPROM) CMOS EPROM
Supply Voltage (VCC) 4.5 V to 5.5 V 5 V
I/O Standard TTL-compatible β€”
Package JLCC-68 (J-Lead Ceramic Chip Carrier) PGA (Pin Grid Array, ceramic)
Operating Temperature [DATA_NEEDED: commercial/industrial/military grade] -40 C to +85 C (extended commercial)
Mounting Type Surface Mount Through-Hole / Socketed
RoHS Status Non-compliant (ceramic JLCC, contains lead) [DATA_NEEDED: RoHS status]
Device Type β€” CPLD (Complex Programmable Logic Device)
Interconnect β€” Programmable Interconnect Array (PIA)
Configuration Memory β€” On-chip EPROM (non-volatile)
Boundary Scan β€” JTAG / IEEE 1149.1

Datasheets & Resources

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