EPM5130LC vs EPM5130WC-2 Comparison
Detailed side-by-side comparison of EPM5130LC by Altera and EPM5130WC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5130LC | EPM5130WC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.60 | $62.00 |
| Series | MAX 5000 | β |
| Family | MAX 5000 (EPM51xx) | β |
| Macrocells | 128 | β |
| Logic Array Blocks (LABs) | 8 | β |
| User I/O Pins | 48 | β |
| Total Inputs (Dedicated + I/O) | 68 | β |
| Dedicated Inputs | 19 | 19 |
| Propagation Delay (tPD) | 55 ns | 45 ns |
| Maximum Internal Clock Frequency | 50 MHz | β |
| Global Clock Inputs | 1 | β |
| Configuration Technology | UV-Erasable / OTP EPROM | β |
| Process Technology | CMOS (0.7 um EPROM) | CMOS |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | 4.75 V to 5.25 V |
| I/O Standard | TTL-compatible | β |
| Package | JLCC-68 (J-Lead Ceramic Chip Carrier) | β |
| Operating Temperature | [DATA_NEEDED: commercial/industrial/military grade] | 0 Β°C to 70 Β°C (Commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Non-compliant (ceramic JLCC, contains lead) | [DATA_NEEDED: RoHS status] |
| Device Family | β | MAX 5000 |
| Product Type | β | UV-Erasable PLD (CPLD) |
| Macrocell Count | β | 128 |
| User I/O Lines | β | 48 |
| Total Inputs (I/O + dedicated) | β | 68 |
| Package Type | β | 100-terminal Ceramic CQFP (R-CQFP-G100), windowed, gull-wing |
| Terminal Pitch | β | 0.650 mm |
| Configuration Memory | β | UV-erasable CMOS EEPROM cells |
| Speed Grade | β | -2 (45 ns) |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |
| Logic Elements | β | AND/OR array with programmable macrocell register |