EPM5130WM883B-1 vs EPM5130WC-1 Comparison
Detailed side-by-side comparison of EPM5130WM883B-1 by Altera and EPM5130WC-1 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5130WM883B-1 - 128-Macrocell UV PLD, 5V, CQFP-100 | Altera MAX 5000
EPM5130WM883B-1 ObsoleteIntel
EPM5130WC-1 - 128-Macrocell 40ns UV CPLD, 100-pin CQFP | Intel (Altera) MAX 5000
EPM5130WC-1 ObsoleteSpecification Comparison
| Parameter | EPM5130WM883B-1 | EPM5130WC-1 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $128.00 | $85.00 |
| Device Family | MAX 5000 (Classic EPLD) | β |
| Manufacturer | Altera (now Intel PSG) | Altera (now Intel) |
| Logic Type | UV-Erasable Programmable Logic Device (EPLD) | β |
| Technology | CMOS, EPROM cell | β |
| Macrocells | 128 | β |
| Logic Array Blocks (LABs) | 8 | β |
| Dedicated Inputs | 19 | β |
| I/O Pins | 48 (bi-directional) | β |
| Propagation Delay (tPD) | 55 ns | β |
| Maximum Clock Frequency (fMAX) | 33.3 MHz | β |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | β |
| External Clock Inputs | 1 global + shared inputs | β |
| Interconnect | Programmable Interconnect Array (PIA) | β |
| Package Type | CQFP-100, ceramic windowed (WM) | 100-pin Ceramic QFP (Windowed) |
| Military Screening | MIL-STD-883 Class B (883B suffix) | β |
| Operating Temperature | [DATA_NEEDED: military/industrial temperature grade] | [DATA_NEEDED: operating temperature range] |
| Programming Method | UV erase + EPROM programming | β |
| RoHS Status | [DATA_NEEDED: confirmed RoHS for ceramic windowed CQFP] | [DATA_NEEDED: RoHS compliance] |
| Mounting Type | Surface Mount (CQFP with J-leads) | Surface Mount |
| Series | β | MAX 5000 |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macrocell Count | β | 128 |
| Logic Array Blocks | β | Multiple LABs (per MAX 5000 architecture) |
| Propagation Delay (tpd) | β | 40 ns |
| Maximum Clock Frequency | β | 50 MHz |
| Erasure Method | β | UV (ultraviolet, windowed package) |
| Process Technology | β | CMOS EPROM |
| User I/O Pins | β | Up to 100 |
| Supply Voltage | β | [DATA_NEEDED: VCC nominal] |
| Programmable | β | Yes (UV-erasable, non-volatile) |
| Logic Family | β | MAX 5000 (Altera) |
| Configuration Memory | β | EPROM (on-chip) |